1. Field of the Invention
The present invention relates to a driving circuit and a display comprising the same, and more particularly, it relates to a driving circuit having a differential circuit and a display comprising the same.
2. Description of the Background Art
A driving circuit having a differential circuit is known in general. Such a driving circuit is employed for writing analog data in data lines of a pixel part in a display such as a liquid crystal display (LCD) or an organic EL (electroluminescence) display, for example. Throughout the specification, the display is described with reference to a liquid crystal display (LCD).
Demand for a miniature LCD employing polysilicon TFTs (thin film transistors) is recently increased. Following this, reduction of power consumption in a display system including an LCD panel and n external control IC and implementation of a digital interface corresponding to digitization of a peripheral device are strongly required.
In particular, digitization of a video signal is highly required. In order to digitize a video signal, a DAC (digital-to-analog converter) circuit converting the digital video signal to an analog video signal must be built into the panel. It is known that a circuit for driving data lines when writing analog data converted from digital data by the DAC circuit is provided.
FIG. 10 is a circuit diagram showing a conventional push-pull differential amplification circuit driving a TFT-LCD panel disclosed in Y. C. Sung et. al., “A Low-Power Data Driver for TFT-LCDs”, SID Digest 12.2 (2000), pp. 142–145.
The conventional push-pull differential amplification circuit shown in FIG. 10 comprises a differential circuit 101, a voltage level shifting circuit 102 and a push-pull output circuit 103. The differential circuit 101 includes a p-channel transistor 113 having a gate supplied with an input in and a p-channel transistor 112 having a gate supplied with an output OUT.
The voltage level shifting circuit 102 has a circuit structure formed by parallel-connecting a p-channel transistor MP1 and an n-channel transistor MN1 to an intermediate portion of a current mirror circuit.
The push-pull output circuit 103 includes a p-channel transistor 131 and an n-channel transistor 132. Nodes VGP and VGN of the voltage level shifting circuit 102 are connected to the gates of the p-channel transistor 131 and the n-channel transistor 132 respectively.
The p-channel transistors 112 and 113 of the differential circuit 101 are connected to a node VO and the node VGN of the voltage level shifting circuit 102 respectively.
In schematic operation of the conventional push-pull differential amplification circuit having the aforementioned structure, the potentials of the nodes VGN and VO are set to the same value when there is no potential difference between the input in and the output OUT.
In a stationary state, mirror currents I1 and I2 regularly flow in the voltage level shifting circuit 102 thereby setting the potentials of the nodes VNG and VGP. When potential difference is caused between the input in and the output OUT, a signal is transmitted to the node VGN or VO thereby causing potential difference between the nodes VGN and VO. The voltage level shifting circuit 102 operates to eliminate the potential difference between the nodes VGN and VO, i.e., to equalize the mirror currents I1 and I2 with each other. Consequently, both of the nodes VGN and VGP are level-shifted to a higher or lower potential side. The push-pull output circuit 103 outputs a signal potential responsive to the potential fluctuation of the nodes VGN and VGP resulting from the operation of the voltage level shifting circuit 103 to an output terminal OUT.
When the output potential OUT is higher than an input potential Vin, the push-pull differential amplification circuit operates to turn off the p-channel transistor 131 of the push-pull output circuit 103 while turning on the n-channel transistor 132 of the push-pull output circuit 103, thereby pulling down the output potential OUT. When the output potential OUT is lower than the input potential Vin, the push-pull differential amplification circuit operates to turn on the p-channel transistor 131 of the push-pull output circuit 103 while turning off the n-channel transistor 132 of the push-pull output circuit 103, thereby pulling up the output potential OUT. In other words, the push-pull differential amplification circuit operates to equalize the input potential Vin and the output potential OUT with each other.
Thus, the conventional push-pull differential amplification circuit operates to reduce the difference between the input potential Vin and the output potential OUT while comparing the same with each other.
In the aforementioned conventional push-pull differential amplification circuit, a bias potential Bias is applied to the gates of the p-channel transistor MP1 and the n-channel transistor MN1 of the voltage level shifting circuit 102 in order to reduce power consumption in the circuit operation, thereby reducing the quantities of the mirror currents I1 and I2 and attaining low power consumption.
In general, the bias potential Bias is set to a level between power supply voltages VDD and VSS (GND). In the conventional circuit shown in FIG. 10, therefore, the bias potential Bias is conceivably set between the potentials of the nodes VGP and VGN. This is because the mirror currents I1 and I2 must be fed by setting the bias potential Bias to the level between the potentials of the nodes VGP and VGN, which is higher than the threshold voltages of the p-channel transistor MP1 and the n-channel transistor MN1, for necessarily turning on the p-channel transistor MP1 and the n-channel transistor MN1 in order to operate the voltage level shifting circuit 102.
Consider a stationary state where the mirror currents I1 and I2 are balanced with each other (the voltages OUT and in are balanced with each other). At this time, the potential of the node VGP is necessarily lower than the threshold voltage of a p-channel transistor connected to the power supply voltage VDD, while the potential of the node VGN is necessarily higher than the threshold voltage of an n-channel transistor connected to the power supply voltage VSS. In this state, both of the p-channel transistor 131 and the n-channel transistor 132 of the push-pull output circuit 103 are ON followed by through currents. It is understood that this relation between the voltage level shifting circuit 102 and the push-pull output circuit 103 is therefore unsuitable for reduction of current consumption. In order to implement low current consumption in this circuit structure, current drivability of the p-channel transistor 131 and the n-channel transistor 132 of the push-pull output circuit 103 may be reduced. In this case, however, drivability for serving as an output stage is reduced, leading to a problem in high-speed operation. In the structures of the voltage level shifting circuit 102 and the push-pull output circuit 103 of the conventional push-pull differential amplification circuit shown in FIG. 10, therefore, it is difficult to reduce current consumption.
In order to feed the mirror currents I1 and I2 in the conventional voltage level shifting circuit 102 shown in FIG. 10, the power supply voltage VDD must satisfy the following inequality:VDD>2(Vtp+Vtn)  (1)where Vtp and Vtn represent the threshold voltages of the p-channel transistor MP1 and the n-channel transistor MN1 respectively. When the conventional push-pull differential amplification circuit shown in FIG. 10 is designed with thin film transistors having high threshold voltages with large dispersion in fabrication, the power supply voltage VDD must be set high due to the limitation of the inequality (1). Consequently, it is disadvantageously difficult to lower the power supply voltage VDD.
In the voltage level shifting circuit 102 of the conventional push-pull differential amplification circuit, further, the power supply voltage VDD is influenced by the threshold voltages of two n-channel transistors and two p-channel transistors, i.e., four transistors in total as shown in the above inequality (1). When the potentials of the nodes VGP and VGN of the voltage level shifting circuit 102 are supplied to the gates of the p-channel transistor 131 and the n-channel transistor 132 of the push-pull output circuit 103 respectively, therefore, the voltage ranges available for the gates of the p-channel transistor 131 and the n-channel transistor 132 are disadvantageously reduced. Therefore, the operating ranges of the p-channel transistor 131 and the n-channel transistor 132 are also reduced, and hence it is difficult to strongly and quickly turn on the p-channel transistor 131 and the n-channel transistor 132 for improving response characteristics. Consequently, the output value of the push-pull output circuit 103 is unstabilized by overshooting or undershooting, and hence it is difficult to improve the precision of the output value. In addition, it takes time to converge the output value, and hence it is also difficult to increase the operating speed.
In general, the operating ranges of the p-channel transistor 131 and the n-channel transistor 132 must be widened in order to prevent such disadvantages, and hence the voltage ranges available for the gates of the p-channel transistor 131 and the n-channel transistor 132 must be widened by increasing the power supply voltage VDD. In the conventional push-pull differential amplification circuit, therefore, it is difficult to implement voltage reduction.